Volkan Kursun
Information Technology Innovation Laboratory
Publications
Citations to my papers and patents: follow this link
Authored BookS 1. V. Kursun and E. G. Friedman, 多电压CMOS电路设计, China Machine Press, June 2008, ISBN 9787111238645. 2. V. Kursun and E. G. Friedman, MultiVoltage CMOS Circuit Design, 242 pp., John Wiley & Sons Ltd., August 2006, ISBN 0470010231.
Book CHAPTERS 1. S. M. Salahuddin and V. Kursun, Data stability and write ability enhancement techniques for FinFET SRAM circuits, NanoCMOS and PostCMOS Electronics: Circuits and Design, Edited by S. P. Mohanty and A. Srivastava, The Institute of Engineering and Technology (IET), pp. 113140, April 2016, ISBN: 9781849199995. 2. H. Jiao and V. Kursun, Trimode Operation for Noise Reduction and Data Preservation in LowLeakage MultiThreshold CMOS Circuits, VLSISoC: ForwardLooking Trends in IC and Systems Design, J. L. Ayala, D. A. Atienza, and R. Reis, (Eds.), Springer, pp. 258290, 2012, ISBN 9783642285653.
Journal Papers 1. A. K. Gundu and V. Kursun, Low leakage clock tree with dualthresholdvoltage split inputoutput repeaters, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 27, No. 7, pp. 15371547, July 2019. 2. Y. Sun, W. He, Z. Mao, H. Jiao, and V. Kursun, MetallicCNremovaltolerant highyield sixCNMOSFET SRAM cell for carbonbased embedded memory, IEEE Transactions on Electron Devices, Vol: 65, Issue: 3, pp. 12301238, March 2018. 3. Y. Sun, W. He, Z. Mao, and V. Kursun, Variable strength keeper for highspeed and lowleakage carbon nanotube domino logic, Microelectronics Journal, Vol. 62, pp. 1220, April 2017. 4. Y. Sun, W. He, Z. Mao, H. Jiao, and V. Kursun, Highyield and robust 9T SRAM cell tolerant to removal of metallic carbon nanotubes, IEEE Transactions on Device and Materials Reliability, Vol. 17, Issue: 1, pp. 2031, March 2017. 5. H. Jiao, Y. Qiu, and V. Kursun, Variabilityaware 7T SRAM circuit with low leakage high data stability SLEEP mode, Integration, the VLSI Journal, Vol. 53, pp. 6879, March 2016. 6. H. Jiao, Y. Qiu, and V. Kursun, Low power and robust memory circuits with asymmetrical ground gating, Microelectronics Journal, Vol. 48, pp. 109119, February 2016. 7. S. M. Salahuddin and V. Kursun, Write assist SRAM cell with asymmetrical bitline access transistors for enhanced data stability and write ability, Journal of Circuits, Systems, and Computers, Vol. 25, No. 1, pp. 119, January 2016. 8. S. M. Salahuddin, H. Jiao, and V. Kursun, FinFET SRAM cells with asymmetrical bitline access transistors for enhanced read stability, Transactions on Electrical and Electronic Materials, Vol. 16, No. 6, pp. 293302, December 2015. 9. Y. Sun, H. Jiao, and V. Kursun, A novel robust and lowleakage SRAM cell with nine carbon nanotube transistors, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 9, pp. 17291739, September 2015. 10. H. Jiao and V. Kursun, Mode Transition Timing and Energy Overhead Analysis in NoiseAware MTCMOS Circuits, Microelectronics Journal, Vol. 45, Issue 8, pp. 11251131, August 2014. 11. H. Zhu and V. Kursun, Novel LowLeakage and HighSpeed TripleThresholdVoltage Buffers with Skewed Inputs and Outputs, IEEE Transactions on Circuits and Systems I, Vol. 61, No. 7, pp. 20132021, July 2014. 12. H. Zhu and V. Kursun, A Comprehensive Comparison of Data Stability Enhancement Techniques with Novel Nanoscale SRAM Cells Under Parameter Fluctuations, IEEE Transactions on Circuits and Systems I, Vol. 61, No. 5, pp. 14731484, May 2014. 13. Y. Sun and V. Kursun, Carbon Nanotubes Blowing New Life into NP Dynamic CMOS Circuits, IEEE Transactions on Circuits and Systems I, Vol. 61, No. 2, pp. 420428, February 2014. 14. H. Jiao and V. Kursun, Reactivation Noise Suppression with Sleep Signal Slew Rate Modulation in MTCMOS Circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, No. 3, pp. 533545, March 2013. 15. H. Jiao and V. Kursun, Threshold Voltage Tuning for Faster Activation with Lower Noise in TriMode MTCMOS Circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 20, Number 4, pp. 741745, April 2012. 16. H. Jiao and V. Kursun, "Ground Bouncing Noise Suppression Techniques for Data Preserving Sequential MTCMOS Circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 19, Number 5, pp. 763773, May 2011. 17. Y. Sun and V. Kursun, NType CarbonNanotube MOSFET Device Profile Optimization for Very Large Scale Integration, Transactions on Electrical and Electronic Materials, Vol. 12, No. 2, pp. 4350, April 2011. 18. H. Jiao and V. Kursun, NoiseAware Data Preserving Sequential MTCMOS Circuits with Dynamic Forward Body Bias, Journal of Circuits, Systems, and Computers (Special Issue on Green Integrated Circuits and Systems, INVITED PAPER), Vol. 20, No. 1, pp. 125145, February 2011. 19. S. A. Tawfik and V. Kursun, MultiThreshold Voltage FinFET Sequential Circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 19, Number 1, pp. 151156, January 2011. 20. H. Jiao and V. Kursun, "Ground Bouncing Noise Aware Combinational MTCMOS Circuits, IEEE Transactions on Circuits and Systems I, Vol. 57, No. 8, pp. 20532065, August 2010. 21. H. Jiao and V. Kursun, LowLeakage and Compact Registers with EasySleep Mode, Journal of LowPower Electronics, Vol. 6, No. 2, pp. 263279, August 2010. 22. S. A. Tawfik and V. Kursun, Dual Supply Voltages and Dual Clock Frequencies for Lower Clock Power and Suppressed TemperatureGradient Induced Clock Skew, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 18, Number 3, pp. 347355, March 2010. 23. S. A. Tawfik and V. Kursun, Robust FinFET Memory Circuits with PType Data Access Transistors for Higher Integration Density and Reduced Leakage Power, Journal of LowPower Electronics, Volume 5, Number 4, pp. 497508, December 2009. 24. S. A. Tawfik and V. Kursun, FinFET Domino Logic with Independent Gate Keepers, Microelectronics Journal, Volume 40, Issue 11, pp. 15311540, November 2009. 25. R. Kumar and V. Kursun, TemperatureAdaptive Voltage Scaling for Enhanced Energy Efficiency in Subthreshold Memory Arrays, Microelectronics Journal, Volume 40, Issue 6, pp. 10131025, June 2009. 26. S. A. Tawfik and V. Kursun, Low Power and High Speed Multi Threshold Voltage Interface Circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 17, Number 5, pp. 638645, May 2009. 27. R. Kumar and V. Kursun, TemperatureAdaptive Voltage Tuning for Enhanced Energy Efficiency in UltraLowVoltage Circuits, Microelectronics Journal, Volume 39, Issue 12, pp. 17141727, December 2008. 28. S. A. Tawfik and V. Kursun, Clock Distribution Networks with Gradual Signal Transition Time Relaxation for Reduced Power Consumption, Journal of Circuits, Systems, and Computers, Volume 17, Number 6, pp. 1173  1191, December 2008. 29. R. Kumar and V. Kursun, TemperatureAdaptive Energy Reduction Techniques for NanoCMOS Circuits Displaying Reversed Temperature Dependence, Journal of Circuits, Systems, and Computers, Volume 17, Number 3, pp. 423438, July 2008. 30. R. Kumar, Z. Liu, and V. Kursun, Technique for Accurate Power and Energy Measurement with the ComputerAided Design Tools, Journal of Circuits, Systems, and Computers, Volume 17, Number 3, pp. 399421, July 2008. 31. Z. Liu and V. Kursun, Characterization of a Novel Nine Transistor SRAM Cell, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 16, Number 4, pp. 488492, April 2008. Ranked 10th in the total number of downloads from IEEE Xplore among all 2008 TVLSI publications. 32. S. A. Tawfik and V. Kursun, LowPower and Compact Sequential Circuits with IndependentGate FinFETs, IEEE Transactions on Electron Devices, Volume 55, Number 1, pp. 6070, January 2008. 33. Z. Liu and V. Kursun, PMOSOnly Sleep Switch DualThreshold Voltage Domino Logic in Sub65nm CMOS Technologies, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 15, Number 12, pp. 13111319, December 2007. 34. R. Kumar and V. Kursun, Voltage Optimization for Simultaneous Energy Efficiency and Temperature Variation Resilience in CMOS Circuits, Microelectronics Journal, Volume 38, Issues 45, pp. 583594, April/May 2007. 35. R. Kumar and V. Kursun, Reversed Temperature Dependent Propagation Delay Characteristics in Nanometer CMOS Circuits, IEEE Transactions on Circuits and Systems II, Volume 53, Number 10, pp. 1078 1082, October 2006. 36. Z. Liu and V. Kursun, Leakage Biased PMOS Sleep Switch Dynamic Circuits, IEEE Transactions on Circuits and Systems II, Volume 53, Number 10, pp. 1093 1097, October 2006. 37. Z. Liu and V. Kursun, Leakage Power Characteristics of Dynamic Circuits in Nanometer CMOS Technologies, IEEE Transactions on Circuits and Systems II, Volume 53, Number 8, pp. 692696, August 2006. 38. Z. Liu and V. Kursun, Sleep Switch Dual Threshold Voltage Domino Logic with Reduced Subthreshold and Gate Oxide Leakage Current, Microelectronics Journal, Volume 37, Issue 8, pp. 812820, August 2006. 39. V. Kursun, V. K. De, E. G. Friedman, and S. G. Narendra, Monolithic Voltage Conversion in Low Voltage CMOS Technologies, Microelectronics Journal, Volume 36, Issue 9, pp. 863867, September 2005. 40. V. Kursun, S. G. Narendra, V. K. De, and E. G. Friedman, Cascode Monolithic DCDC Converter for Reliable Operation at High Input Voltages, International Journal of Analog Integrated Circuits and Signal Processing, Volume 42, Number 3, pp. 231238, March 2005. 41. V. Kursun, S. G. Narendra, V. K. De, and E. G. Friedman, Low Voltage Swing Monolithic DCDC Conversion, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Volume 51, Number 5, pp. 241248, May 2004. In the top15 most downloaded TCASII papers list from IEEE Xplore for two consecutive years, 2004 and 2005. 42. V. Kursun and E. G. Friedman, Sleep Switch Dual Threshold Voltage Domino Logic with Reduced Standby Leakage Current, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 12, Number 5, pp. 485496, May 2004. 43. D. H. Albonesi, R. Balasubramonian, S. G. Dropsho, S. Dwarkadas, E. G. Friedman, M. C. Huang, V. Kursun, G. Magklis, M. L. Scott, G. Semeraro, P. Bose, A. Buyuktosunoglu, P. W. Cook, and S. E. Schuster, Dynamically Tuning Processor Resources with Adaptive Processing, IEEE Computer, Volume 36, Number 12, pp. 4958, December 2003. 44. V. Kursun and E. G. Friedman, Domino Logic with Variable Threshold Voltage Keeper, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 11, Number 6, pp. 10801093, December 2003. 45. V. Kursun, S. G. Narendra, V. K. De, and E. G. Friedman, Analysis of Buck Converters for OnChip Integration with a Dual Supply Voltage Microprocessor, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 11, Number 3, pp. 514522, June 2003.
Conference Papers 1. A. K. Gundu and V. Kursun, Energy efficient clock distribution with lowleakage multiVt buffers, Proceedings of the IEEE International Symposium on Power and Timing, Modeling, Optimization and Simulation, July 2019. 2. Y. Sun, W. He, Z. Mao, H. Jiao, and V. Kursun, Statistical modeling and design of a 16nm 9T SRAM Cell considering postsynthesis removal of metalliccarbonnanotubes, Proceedings of the IEEE International Conference on Electronics, Information, and Communication, January 2019. 3. Y. Sun, W. He, Z. Mao, H. Jiao, and V. Kursun, Metalliccarbonnanotuberemoval tolerant SRAM cell with 9 transistors, Proceedings of the IEEE International Conference on ASIC, October 2017. 4. H. Jiao, Y. Qiu, and V. Kursun, VariationsTolerant 9T SRAM Circuit with Robust and Low Leakage SLEEP Mode, Proceedings of the IEEE International Symposium on OnLine Testing and Robust System Design, July 2016. 5. S. M. Salahuddin and V. Kursun, Asymmetrical FinFET SRAM cells with wider read noise margin and lower leakage currents, Proceedings of the IEEE TENCON, November 2015. 6. Y. Sun and V. Kursun, Carbonbased sleep switch dynamic logic circuits with variable strength keeper for lowerleakage currents and higherspeed, Proceedings of the IEEE International Symposium on Circuits and Systems, May 2015. 7. H. Zhu and V. Kursun, 2phase highfrequency clock distribution with SPLITIO dualVt repeaters for suppressed leakage currents, Proceedings of the IEEE International Symposium on Circuits and Systems, May 2015. 8. Y. Sun, H. Jiao, and V. Kursun, Lowleakage 9CNMOSFET SRAM cell with enhanced read and write voltage margins, Proceedings of the IEEE International Conference on Microelectronics, December 2014. Best Paper Award First Place. 9. H. Zhu and V. Kursun, Triplethresholdvoltage 9transistor SRAM cell for data stability and energyefficiency at ultralow power supply voltages, Proceedings of the IEEE International Conference on Microelectronics, December 2014. 10. S. M. Salahuddin and V. Kursun, Highspeed and lowleakage FinFET SRAM cell with enhanced read and write voltage margins, Proceedings of the IEEE International Symposium on Integrated Circuits, December 2014. 11. H. Zhu and V. Kursun, A Comprehensive Comparison of Superior TripleThresholdVoltage 7Transistor, 8Transistor, and 9Transistor SRAM Cells, Proceedings of the IEEE International Symposium on Circuits and Systems, May 2014. 12. S. M. Salahuddin and V. Kursun, Underlap Engineered EightTransistor SRAM Cell for Enhanced Write Ability and Suppressed Leakage Power Consumption, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, December 2013. 13. Y. Sun and V. Kursun, A Comparison of HighFrequency 32bit Dynamic Adders with Conventional Silicon and Novel Carbon Nanotube Transistor Technologies, Proceedings of the IEEE International Systems on Chip (SoC) Design Conference, November 2013. 14. H. Jiao and V. Kursun, Novel High Electrical Quality SevenTransistor Memory Cell with Asymmetrical Ground Gating, Proceedings of the IEEE International Systems on Chip (SoC) Design Conference, November 2013 (INVITED PAPER). 15. H. Jiao and V. Kursun, Characterization of Mode Transition Timing Overhead for Net Energy Savings in LowNoise MTCMOS Circuits, Proceedings of the IEEE International Conference on VLSI and SystemonChip (VLSISoC), October 2013. 16. K. Sarfraz and V. Kursun, Characterization of a Low Leakage Current and HighSpeed 7T SRAM Circuit with Wide Voltage Margins, Proceedings of the IEEE Computer Society Annual Symposium on VLSI, August 2013. 17. H. Jiao and V. Kursun, Ground Gated 8T SRAM Cells with Enhanced Read and Hold Data Stability, Proceedings of the IEEE Computer Society Annual Symposium on VLSI, August 2013. 18. S. M. Salahuddin, H. Jiao, and V. Kursun, Characterization of FinFET SRAM Cells with Asymmetrically Gate Underlapped Bitline Access Transistors under Process Parameter Fluctuations, Proceedings of the IEEE International Conference on Electron Devices and SolidState Circuits, June 2013. 19. Y. Sun and V. Kursun, LowPower and Compact NP Dynamic CMOS Adder with 16nm Carbon Nanotube Transistors, Proceedings of the IEEE International Symposium on Circuits and Systems, May 2013. 20. H. Zhu and V. Kursun, Novel DualThresholdVoltage EnergyEfficient Buffers for Driving Large Extrinsic Load Capacitance, Proceedings of the IEEE International Symposium on Circuits and Systems, May 2013. 21. S. M. Salahuddin, H. Jiao, and V. Kursun, LowLeakage Hybrid FinFET SRAM Cell with Asymmetrical Gate Overlap / Underlap Bitline Access Transistors for Enhanced Read Data Stability, Proceedings of the IEEE International Symposium on Circuits and Systems, May 2013. 22. H. Zhu and V. Kursun, Impact of Process Parameter and Supply Voltage Fluctuations on MultiThresholdVoltage SevenTransistor Static Memory Cells, Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design, March 2013. 23. S. M. Salahuddin, H. Jiao, and V. Kursun, A Novel 6T SRAM Cell with Asymmetrically Gate Underlap Engineered FinFETs for Enhanced Read Data Stability and Write Ability, Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design, March 2013. 24. H. Jiao and V. Kursun, Characterization of NoiseAware MTCMOS Circuits with Sleep Signal Slew Rate Modulation under Process Parameter Variations, Proceedings of the International Conference on Electronics, Information and Communication, January 2013. 25. H. Jiao and V. Kursun, MultiPhase Sleep Signal Modulation for Mode Transition Noise Mitigation in MTCMOS Circuits, Proceedings of the IEEE International Systems on Chip (SoC) Design Conference, November 2012 (ISOCC 2012 IEEK SoC Design Group Award). 26. Y. Sun and V. Kursun, NP Dynamic CMOS Resurrection with Carbon Nanotube Field Effect Transistors, Proceedings of the IEEE International Systems on Chip (SoC) Design Conference, November 2012. 27. H. Jiao and V. Kursun, 'Low Power and Robust Ground Gated Memory Banks with Combined Write Assist Techniques, Proceedings of the IEEE Low Voltage Low Power Conference (Faible Tension Faible Consommation  FTFC), June 2012. 28. H. Zhu and V. Kursun, Novel TripleThresholdVoltage EightTransistor SRAM Circuit with Enhanced Overall Electrical Quality, Proceedings of the IEEE Low Voltage Low Power Conference (Faible Tension Faible Consommation  FTFC), June 2012. 29. H. Jiao and V. Kursun, FullCustom Design of Low Leakage Data Preserving Ground Gated 6T SRAM Cells to Facilitate SingleEnded Write Operations, Proceedings of the IEEE International Symposium on Circuits and Systems, May 2012. 30. H. Zhu and V. Kursun, Symmetrical TripleThresholdVoltage NineTransistor SRAM Circuit with Superior Noise Immunity and Overall Electrical Quality, Proceedings of the IEEE International Systems on Chip (SoC) Design Conference, November 2011 (INVITED PAPER). 31. Y. Sun and V. Kursun, Uniform Carbon Nanotube Diameter and Nanoarray Pitch for VLSI of 16nm Pchannel MOSFETs, Proceedings of the IEEE International Conference on VLSI and SystemonChip (VLSISoC), October 2011. 32. H. Jiao and V. Kursun, Sleep Signal Slew Rate Modulation for Mode Transition Noise Suppression in Ground Gated Integrated Circuits, Proceedings of the IEEE International Systems on Chip (SOC) Conference, September 2011. 33. Y. Sun and V. Kursun, Substrate Bias Considerations for Low Leakage 16nm PChannel Carbon Nanotube Transistors, Proceedings of the IEEE International Midwest Symposium on Circuits and Systems, August 2011. 34. Y. Sun and V. Kursun, Uniform Diameter and Pitch CoDesign of 16nm Ntype Carbon Nanotube Channel Arrays for VLSI, Proceedings of the IEEE Asia Symposium on Quality Electronic Design, July 2011. 35. H. Zhu and V. Kursun, ApplicationSpecific Selection of 6T SRAM Cells Offering Superior Performance and Quality with a TripleThresholdVoltage CMOS Technology, Proceedings of the IEEE Asia Symposium on Quality Electronic Design, July 2011. 36. Y. Sun and V. Kursun, Leakage Current and Bottom Gate Voltage Considerations in Developing Maximum Performance 16nm NChannel Carbon Nanotube Transistors, Proceedings of the IEEE International Symposium on Circuits and Systems, May 2011. 37. H. Jiao and V. Kursun, Asymmetrical Ground Gating for Low Leakage and Data Robust Sleep Mode in Memory Banks, Proceedings of the IEEE International Symposium on VLSI Design, Automation, and Test, April 2011. 38. Y. Sun and V. Kursun, Physical Parametric Analysis of 16nm NChannel CarbonNanotube Transistors for Manufacturability, Proceedings of the IEEE International Conference on Microelectronics, December 2010. 39. H. Zhu and V. Kursun, Data Stability Enhancement Techniques for Nanoscale Memory Circuits: 7T Memory Design Tradeoffs and Options in 80nm UMC CMOS Technology, Proceedings of the IEEE International Systems on Chip (SoC) Design Conference, November 2010 (INVITED PAPER). 40. Y. Sun and V. Kursun, 16nm Ptype Carbon Nanotube MOSFET Device Profile Optimization for HighSpeed, Proceedings of the IEEE International Systems on Chip (SoC) Design Conference, November 2010 (INVITED PAPER). 41. H. Jiao and V. Kursun, Power Gated SRAM Circuits with Data Retention Capability and High Immunity to Noise: A Comparison for Reliability in Low Leakage Sleep Mode, Proceedings of the IEEE International Systems on Chip (SoC) Design Conference, November 2010 (INVITED PAPER). 42. H. Jiao and V. Kursun, How Forward Body Bias Helps to Reduce Mode Transition Noise and Silicon Area in MTCMOS Circuits: Divulging the Basic Mechanism, Proceedings of the IEEE International Systems on Chip (SoC) Design Conference, November 2010 (INVITED PAPER). 43. H. Jiao and V. Kursun, Reactivation Noise Suppression with Threshold Voltage Tuning in Sequential MTCMOS Circuits, Proceedings of the IEEE International Conference on VLSI and SystemonChip (VLSISoC), September 2010. 44. H. Jiao and V. Kursun, HighSpeed and LowLeakage MTCMOS Memory Registers, Proceedings of the IEEE Asia Symposium on Quality Electronic Design, August 2010. 45. H. Jiao and V. Kursun, Dynamic Forward Body Bias Enhanced TriMode MTCMOS, Proceedings of the IEEE Asia Symposium on Quality Electronic Design, August 2010. 46. H. Jiao and V. Kursun, Smooth Awakenings: Reactivation Noise Suppressed LowLeakage and Robust MTCMOS FlipFlops, Proceedings of the IEEE International Symposium on Circuits and Systems, May 2010. 47. H. Jiao and V. Kursun, Ground Bouncing Noise Aware Sequential MTCMOS Circuits with Data Retention Capability, Proceedings of the IEEE International Symposium on Integrated Circuits, December 2009 (INVITED PAPER). 48. S. A. Tawfik and V. Kursun, LowPower and Robust SixFinFET Memory Cell Using Selective GateDrain/Source Overlap Engineering, Proceedings of the IEEE International Symposium on Integrated Circuits, December 2009 (INVITED PAPER). 49. H. Jiao and V. Kursun, Sleep Transistor Forward Body Bias: an Extra Knob to Lower Ground Bouncing Noise in MTCMOS Circuits, Proceedings of the IEEE International Systems on Chip (SoC) Design Conference, November 2009 (INVITED PAPER). 50. S. A. Tawfik and V. Kursun, Manufacturable LowPower Latches for Standard TiedDoubleGate FinFET Technologies, Proceedings of the IEEE International Midwest Symposium on Circuits and Systems, August 2009. 51. S. A. Tawfik and V. Kursun, FinFET Technology Development Guidelines for Higher Performance, Lower Power, and Stronger Resilience to Parameter Variations, Proceedings of the IEEE International Midwest Symposium on Circuits and Systems, August 2009. 52. H. Jiao and V. Kursun, Ground Bouncing Noise Suppression Techniques for MTCMOS Circuits, Proceedings of the IEEE Asia Symposium on Quality Electronic Design, July 2009. 53. S. A. Tawfik and V. Kursun, Parameter Space Exploration for Robust and HighPerformance nChannel and pChannel Symmetric DoubleGate FinFETs, Proceedings of the IEEE Asia Symposium on Quality Electronic Design, July 2009. 54. S. A. Tawfik and V. Kursun, Mutual Exploration of FinFET Technology and Circuit Design Options for Implementing Compact BruteForce Latches, Proceedings of the IEEE Asia Symposium on Quality Electronic Design, July 2009. 55. S. A. Tawfik and V. Kursun, MultiV_{th} FinFET Sequential Circuits with IndependentGate Bias and WorkFunction Engineering for Reduced Power Consumption, Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, December 2008 (INVITED PAPER). 56. S. A. Tawfik and V. Kursun, Asymmetric DualGate MultiFin Keeper Bias Options and Optimization for Low Power and Robust FinFET Domino Logic, Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, December 2008. 57. S. A. Tawfik and V. Kursun, Stability Enhancement Techniques for Nanoscale SRAM Circuits: A Comparison, Proceedings of the IEEE International Systems on Chip Design Conference, November 2008 (INVITED PAPER). 58. S. A. Tawfik and V. Kursun, Portfolio of FinFET Memories: Innovative Techniques for an Emerging Technology, Proceedings of the IEEE International Systems on Chip Design Conference, November 2008 (INVITED PAPER). 59. R. Kumar and V. Kursun, TemperatureAdaptive Dynamic Voltage Scaling for High Temperature Energy Efficiency in Subthreshold Memory Banks, Proceedings of the IEEE International Midwest Symposium on Circuits and Systems, August 2008. 60. Z. Liu and V. Kursun, Characterization of WakeUp Delay Versus Sleep Mode Power Consumption and Sleep/Active Mode Transition Energy Overhead Tradeoffs in MTCMOS Circuits, Proceedings of the IEEE International Midwest Symposium on Circuits and Systems, August 2008. 61. S. A. Tawfik and V. Kursun, WorkFunction Engineering for Reduced Power and Higher Integration Density: An Alternative to Sizing for Stability in FinFET Memory Circuits, Proceedings of the IEEE International Symposium on Circuits and Systems, May 2008 (INVITED PAPER). 62. S. A. Tawfik and V. Kursun, Dynamic Wordline Voltage Swing for Low Leakage and Stable Static Memory Banks, Proceedings of the IEEE International Symposium on Circuits and Systems, May 2008. 63. S. A. Tawfik and V. Kursun, Low Power and Robust 7T DualVt SRAM Circuit, Proceedings of the IEEE International Symposium on Circuits and Systems, May 2008. 64. S. A. Tawfik and V. Kursun, Characterization of New Static IndependentGateBiased FinFET Latches and FlipFlops under Process Variations, Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design, March 2008. 65. S. A. Tawfik and V. Kursun, Compact FinFET Memory Circuits with PType Data Access Transistors for Low Leakage and Robust Operation, Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design, March 2008. 66. Z. Liu, S. A. Tawfik, and V. Kursun, Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter Fluctuations, Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design, March 2008. 67. S. A. Tawfik, Z. Liu, and V. Kursun, IndependentGate and TiedGate FinFET SRAM Circuits: Design Guidelines for Reduced Area and Enhanced Stability, Proceedings of the IEEE International Conference on Microelectronics, December 2007. 68. S. A. Tawfik and V. Kursun, High Speed FinFET Domino Logic Circuits with Independent GateBiased DoubleGate Keepers Providing Dynamically Adjusted Immunity to Noise, Proceedings of the IEEE International Conference on Microelectronics, December 2007. 69. S. A. Tawfik and V. Kursun, Low Power and Stable FinFET SRAM with Static Independent Gate Bias for Enhanced Integration Density, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, December 2007. 70. Z. Liu and V. Kursun, New MTCMOS FlipFlops with Simple Control Circuitry and Low Leakage Data Retention Capability, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, December 2007. 71. R. Kumar and V. Kursun, TemperatureAdaptive Energy Reduction for UltraLow PowerSupplyVoltage Subthreshold Logic Circuits, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, December 2007. 72. S. A. Tawfik and V. Kursun, Buffer Insertion and Sizing in Clock Distribution Networks with Gradual Transition Time Relaxation for Reduced Power Consumption, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, December 2007. 73. S. A. Tawfik and V. Kursun, LowPower HighPerformance FinFET Sequential Circuits, Proceedings of the IEEE International Systems on Chip (SOC) Conference, September 2007. 74. Z. Liu, S. A. Tawfik, and V. Kursun, An IndependentGate FinFET SRAM Cell for High Data Stability and Enhanced Integration Density, Proceedings of the IEEE International Systems on Chip (SOC) Conference, September 2007. 75. S. A. Tawfik and V. Kursun, Dual Signal Frequencies and Voltage Levels for Low Power and TemperatureGradient Tolerant Clock Distribution, Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, August 2007. 76. Z. Liu and V. Kursun, Low Energy MTCMOS with Sleep Transistor Charge Recycling, Proceedings of the IEEE International Midwest Symposium on Circuits and Systems, August 2007. 77. R. Kumar and V. Kursun, Modeling of Temperature Effects on NanoCMOS Devices with the Predictive Technologies, Proceedings of the IEEE International Midwest Symposium on Circuits and Systems, August 2007. 78. R. Kumar and V. Kursun, TemperatureAdaptive BodyBias and Supply Voltage Scaling for Enhanced Energy Efficiency in NanoCMOS Circuits, Proceedings of the IEEE International Midwest Symposium on Circuits and Systems, August 2007. 79. R. Kumar, Z. Liu, and V. Kursun, Fundamental Concepts of Power and Energy Measurement with the ComputerAidedDesign Tools, Proceedings of the IEEE International Midwest Symposium on Circuits and Systems, August 2007. 80. V. Kursun, S. A. Tawfik, and Z. Liu, LeakageAware Design of Nanometer SoC, Proceedings of the IEEE International Symposium on Circuits and Systems, May 2007 (INVITED PAPER). 81. Z. Liu and V. Kursun, Charge Recycling MTCMOS for Low Energy Active/Sleep Mode Transitions, Proceedings of the IEEE International Symposium on Circuits and Systems, May 2007. 82. Z. Liu and V. Kursun, High Read Stability and Low Leakage Cache Memory Cell, Proceedings of the IEEE International Symposium on Circuits and Systems, May 2007. 83. S. A. Tawfik and V. Kursun, LowPower LowVoltage HotSpot Tolerant Clocking with Suppressed Skew, Proceedings of the IEEE International Symposium on Circuits and Systems, May 2007. 84. S. A. Tawfik and V. Kursun, MultiVth Level Conversion Circuits for MultiVDD Systems, Proceedings of the IEEE International Symposium on Circuits and Systems, May 2007. 85. Z. Liu and V. Kursun, Charge Recycling Between Virtual Power and Ground Lines for Low Energy MTCMOS, Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design, March 2007. 86. S. A. Tawfik and V. Kursun, DualVDD Clock Distribution for Low Power and Minimum Temperature Fluctuations Induced Skew, Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design, March 2007. 87. R. Kumar and V. Kursun, Supply and Threshold Voltage Optimization for Temperature Variation Insensitive Circuit Performance: A Comparison, Proceedings of the IEEE International SystemsonChip (SOC) Conference, September 2006. 88. Z. Liu and V. Kursun, High Read Stability and Low Leakage SRAM Cell Based on Data/Bitline Decoupling, Proceedings of the IEEE International SystemsonChip (SOC) Conference, September 2006. 89. R. Kumar and V. Kursun, Temperature Variation Insensitive Energy Efficient CMOS Circuits in a 65nm CMOS Technology, Proceedings of the IEEE International Midwest Symposium on Circuits and Systems, August 2006. 90. V. Kursun and Z. Liu, WideTemperature Spectrum Low Leakage Dynamic Circuit Technique for Sub65nm CMOS Technologies, Proceedings of the IEEE International Symposium on Circuits and Systems, May 2006. 91. R. Kumar and V. Kursun, Impact of Temperature Fluctuations on Circuit Characteristics in 180nm and 65 nm CMOS Technologies, Proceedings of the IEEE International Symposium on Circuits and Systems, May 2006. 92. Z. Liu and V. Kursun, Leakage Current Starved Domino Logic, Proceedings of the ACM/SIGDA Great Lakes Symposium on VLSI, April 2006. 93. R. Kumar and V. Kursun, A Design Methodology for Temperature Variation Insensitive Low Power Circuits, Proceedings of the ACM/SIGDA Great Lakes Symposium on VLSI, April 2006. 94. Z. Liu and V. Kursun, Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages, Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design, March 2006. 95. Z. Liu and V. Kursun, Leakage Biased Sleep Switch Domino Logic, Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design, March 2006. 96. Z. Liu and V. Kursun, High Speed Low Swing Dynamic Circuits with Multiple Supply and Threshold Voltages, Proceedings of the IEEE Computer Society Annual Symposium on VLSI, March 2006. 97. Z. Liu and V. Kursun, Shifted Leakage Power Characteristics of Dynamic Circuits Due to Gate Oxide Tunneling, Proceedings of the IEEE International Systems on Chip (SOC) Conference, pp. 151154, September 2005. 98. R. Kumar and V. Kursun, Voltage Optimization for Temperature Variation Insensitive CMOS Circuits, Proceedings of the IEEE International Midwest Symposium on Circuits and Systems, August 2005. 99. Z. Liu and V. Kursun, Temperature Dependent Leakage Power Characteristics of Dynamic Circuits in Sub65nm CMOS Technologies, Proceedings of the IEEE International Midwest Symposium on Circuits and Systems, August 2005. 100. Z. Liu and V. Kursun, Bidirectional Dynamic Node Low Voltage Swing Domino Logic, Proceedings of the IEEE International Midwest Symposium on Circuits and Systems, August 2005. 101. V. Kursun, G. Schrom, V. K. De, E. G. Friedman, and S. G. Narendra, Cascode Buffer for Monolithic Voltage Conversion Operating at High Input Supply Voltages, Proceedings of the IEEE International Symposium on Circuits and Systems, May 2005. 102. G. Schrom, P. Hazucha, JaeHong Hahn, V. Kursun, D. Gardner, S. G. Narendra, T. Karnik, and V. De, Feasibility of Monolithic and 3Dstacked DCDC Converters for Microprocessors in 90nm Technology Generation, Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, pp. 263268, August 2004. 103. V. Kursun and E. G. Friedman, Energy Efficient Dual Threshold Voltage Dynamic Circuits Employing Sleep Switches to Minimize Subthreshold Leakage, Proceedings of the IEEE International Symposium on Circuits and Systems, Vol. 2, pp. 417420, May 2004. 104. V. Kursun and E. G. Friedman, Forward Body Biased Keeper for Enhanced Noise Immunity in Domino Logic Circuits, Proceedings of the IEEE International Symposium on Circuits and Systems, Vol. 2, pp. 917920, May 2004. 105. V. Kursun and E. G. Friedman, Node Voltage Dependent Subthreshold Leakage Current Characteristics of Dynamic Circuits, Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design, pp. 104109, March 2004. 106. V. Kursun, S. G. Narendra, V. K. De, and E. G. Friedman, High Input Voltage StepDown DCDC Converters for Integration in a Low Voltage CMOS Process, Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design, pp. 517521, March 2004. 107. V. Kursun and E. G. Friedman, Speed and Noise Immunity Enhanced Low Power Dynamic Circuits, Technical Digest of the Semiconductor Research Corporation (SRC) TECHCON, August 2003. 108. V. Kursun, S. G. Narendra, V. K. De, and E. G. Friedman, Monolithic DCDC Converter Analysis and MOSFET Gate Voltage Optimization, Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design, pp. 279284, March 2003. 109. S. Dropsho, V. Kursun, D. H. Albonesi, S. Dwarkadas, and E. G. Friedman, Managing Static Leakage Energy in Microprocessor Functional Units, Proceedings of the IEEE/ACM International Symposium on Microarchitecture, pp. 321332, November 2002. 110. V. Kursun and E. G. Friedman, Variable Threshold Voltage Keeper for Contention Reduction in Dynamic Circuits, Proceedings of the IEEE International ASIC/SOC Conference, pp. 314318, September 2002. 111. V. Kursun, S. G. Narendra, V. K. De, and E. G. Friedman, Efficiency Analysis of a High Frequency Buck Converter for OnChip Integration with a DualV_{DD} Microprocessor, Proceedings of the European SolidState Circuits Conference, pp. 743746, September 2002. 112. V. Kursun and E. G. Friedman, Domino Logic with Dynamic Body Biased Keeper, Proceedings of the European SolidState Circuits Conference, pp. 675678, September 2002. 113. V. Kursun, R. M. Secareanu, and E. G. Friedman, CMOS Voltage Interface Circuit for Low Power Systems, Proceedings of the IEEE International Symposium on Circuits and Systems, Vol. 3, pp. 667670, May 2002. 114. V. Kursun and E. G. Friedman, Low Swing Dual Threshold Voltage Domino Logic, Proceedings of the ACM/SIGDA Great Lakes Symposium on VLSI, pp. 4752, April 2002. 115. V. Kursun, R. M. Secareanu, and E. G. Friedman, Low Power CMOS BiDirectional Voltage Converter, Proceedings of the IEEE EDS/CAS Activities in Western New York Conference, pp. 67, November 2001.
DISSERTATION V. Kursun, Supply and Threshold Voltage Scaling Techniques in CMOS Circuits, University of Rochester, Rochester, New York, May 2004. Advisor: Professor Eby G. Friedman.

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